Regviz

Silicon Labs /ZGM230SA27HGN /GPIO_NS /MODEM_ROUTEEN

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MODEM_ROUTEEN

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32BG22C224F512GM32/GPIO_NS/MODEM_ROUTEEN#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ANT0PEN)ANT0PEN 0 (ANT1PEN)ANT1PEN 0 (ANTROLLOVERPEN)ANTROLLOVERPEN 0 (ANTRR0PEN)ANTRR0PEN 0 (ANTRR1PEN)ANTRR1PEN 0 (ANTRR2PEN)ANTRR2PEN 0 (ANTRR3PEN)ANTRR3PEN 0 (ANTRR4PEN)ANTRR4PEN 0 (ANTRR5PEN)ANTRR5PEN 0 (ANTSWENPEN)ANTSWENPEN 0 (ANTSWUSPEN)ANTSWUSPEN 0 (ANTTRIGPEN)ANTTRIGPEN 0 (ANTTRIGSTOPPEN)ANTTRIGSTOPPEN 0 (DCLKPEN)DCLKPEN 0 (DOUTPEN)DOUTPEN

Description

MODEM pin enable

Fields

ANT0PEN

ANT0 pin enable control bit
ANT1PEN

ANT1 pin enable control bit
ANTROLLOVERPEN

ANTROLLOVER pin enable control bit
ANTRR0PEN

ANTRR0 pin enable control bit
ANTRR1PEN

ANTRR1 pin enable control bit
ANTRR2PEN

ANTRR2 pin enable control bit
ANTRR3PEN

ANTRR3 pin enable control bit
ANTRR4PEN

ANTRR4 pin enable control bit
ANTRR5PEN

ANTRR5 pin enable control bit
ANTSWENPEN

ANTSWEN pin enable control bit
ANTSWUSPEN

ANTSWUS pin enable control bit
ANTTRIGPEN

ANTTRIG pin enable control bit
ANTTRIGSTOPPEN

ANTTRIGSTOP pin enable control bit
DCLKPEN

DCLK pin enable control bit
DOUTPEN

DOUT pin enable control bit

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data